Advances in semiconductor manufacturing technology have resulted in, among other things, reducing the cost of sophisticated electronics to the extent that integrated circuits have become ubiquitous in the modern environment.
As is well-known, integrated circuits are typically manufactured in batches, and these batches usually contain a plurality of semiconductor wafers within and upon which integrated circuits are formed through a variety of semiconductor manufacturing steps, including, for example, depositing, masking, patterning, implanting, etching, and so on.
Completed wafers are tested to determine which die, or integrated circuits, on the wafer are capable of operating according to predetermined specifications. In this way, integrated circuits that cannot perform as desired are not packaged, or otherwise incorporated into finished products.
Integrated circuits are typically manufactured on roughly circular semiconductor substrates, or wafers. Further, it is common to form such integrated circuits so that conductive regions disposed on, or close to, the uppermost layers of the integrated circuits are available to act as terminals for connection to various electrical elements disposed in, or on, the lower layers of those integrated circuits. In testing, these conductive regions are commonly contacted with a probe card.
In conventional manufacturing processes, subsequent to forming integrated circuits on the wafer, those unsingulated integrated circuits are tested, and the wafer is then thinned and singulated. During the thinning process it is common to attach the topside of the wafer to a carrier wafer to provide mechanical support for the thinning operations.
What is needed are methods and apparatus that enable wafer level testing of integrated circuits subsequent wafer thinning, and subsequent to wafer dicing.